(1) Field of the Invention
The present invention relates to the fabrication of a dynamic random access memory (DRAMs) device, and more particularly a method for fabrication fin-shaped stacked capacitors for DRAM cells using an improved semiconductor process.
(2) Description of the Prior Art
The integrated circuit density on chips diced from semiconductor substrates has dramatically increased in recent years. This increase in density is due to advances in ultra large scale integration (ULSI) technologies. For example, advances in high resolution photolithography using shorter ultra violet (UV) wavelengths have significantly reduced the photoresist minimum image size. Another ULSI technology that has increased the circuit density is anisotropic plasma etching in which the directional etching by ions provides an essentially bias free replication of the photoresist image in the underlying patterned layer, such as in polysilicon, insulating oxides, and metals layers. These advances have come, however, with certain processing problems. For example, the high resolution lithography requires a shallow depth of focus (DOF), and exposing the photoresist over a rough topography results in distorted photoresist images. The patterning of layers by directional etching over rough topography results in incomplete removal of the layer over the steep steps, usually referred to as stringers, rails, or fences because of their appearances under the microscope. However, these and other technological advances are still used on many integrated circuit devices even with these process limitations.
One specific type of integrated circuit device where this high resolution processing is of particular importance is the dynamic random access memory (DRAM) circuit. This DRAM circuit is used extensively in the electronic industry and particularly in the computer industry for electrical data storage. These DRAM circuits consist of an array of individual memory cells, each cell usually consists of a field effect transistor (FET) switch and a single storage capacitor. Information is stored on the cell as charge on the capacitor which represents a unit of data (bit), that is accessed by read/write circuits on the periphery of the chip. By the year 2002 the number of these cells are expected to reach 256 megabits per DRAM chip. To achieve this advance in data storage and still maintain a reasonable chip size, the individual cells on the chip must be significantly reduced in size. As these individual memory cells decrease in size, so must the area on the cell that the storage capacitor occupies. The reduction in the storage capacitor size makes it difficult to store sufficient charge on the capacitor to maintain an acceptable signal-to-noise level, and circuit requires shorter refresh cycle times to retain the necessary charge level.
One method of overcoming this size problem is to build stacked capacitor which extend vertically over the cell areas to increase the electrode capacitor area while confining the capacitor within the cell area. A method of forming a stacked capacitor having fin-shaped electrodes is proposed by Hsue et al, U.S. Pat. No. 5,436,186, in which a multi-layer is made by depositing alternate layers of different insulating material then patterned and selectively etching one type layer to form a fin-shaped template on which is deposited a doped polysilicon for the bottom electrode. Another approach is describe by Chen, U.S. Pat. No. 5,436,188 in which a self-aligned contact opening is etched to the capacitor node contact through two insulating layers (thin and thick) of different materials. The thick layer is recessed under the thin layer and a doped polysilicon layer is used to form the storage capacitor bottom electrode having a serpentine shape.
However, in general these stacked capacitors are built over and on field effect transistor and field oxide isolation regions, and as previously mentioned conformal layers deposited thereon are in general non-planar (rough) topography and can limit the photoresist resolution, and the subsequent directional (anisotropic) etching can leave unwanted residual material (stringers) that reduce product yield and/or degrade the electrical performance. Therefore, there is still a strong need in the semiconductor industry for DRAM processing that circumvent the above problems associated with rough topography.